Process-Variation-Resistant Dynamic Power Optimization for VLSI Circuits
نویسندگان
چکیده
Introduction Introduction Background Background – – Dynamic power dissipation Dynamic power dissipation – – Glitch reduction Glitch reduction – – Previous LP model Previous LP model Process Process-variation variation-resistant LP model resistant LP model – – Process variation Process variation – – Delay model Delay model – – LP model based on worst LP model based on worst-case timing case timing – – LP model based on statistical timing LP model based on statistical timing Input Input-specific optimization specific optimization – – Without process Without process-variation variation – – With process With process-variation variation
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